Measuring Moore’s Law: Evidence from Price, Cost, and Quality Indexes

Abstract

"Moore's Law" in the semiconductor manufacturing industry is used to describe the predictable historical evolution of a single manufacturing technology platform that has been continuously reducing the costs of fabricating electronic circuits since the mid-1960s. Some features of its future evolution were first correctly predicted by Gordon E. Moore in 1965, and Moore's Law became an industry synonym for continuous, periodic reduction in both size and cost for electronic circuit elements. This paper develops develops some stylized economic facts, reviewing why and how this progression in manufacturing technology delivered a 20 to 30 percent annual decline in the cost of manufacturing a transistor, on average, as long as it continued. Other characteristics associated with smaller feature sizes would be expected to have additional economic value, and historical trends for these characteristics are reviewed. Lower manufacturing costs alone pose no special challenges for price and innovation measurement, but these other benefits do, and motivate quality adjustment methods when semiconductor product prices are measured. Empirical evidence of recent changes to the historical Moore's Law trajectory is analyzed, and shows a slowdown in Moore's Law as measured by prices for the highest volume products: memory chips, custom chip designs outsourced to dedicated contract manufacturers (foundries), and Intel microprocessors. Evidence to the contrary, which relates primarily to Intel microprocessors is reviewed, as are economic reasons why Intel microprocessor prices might behave differently from prices for other types of semiconductor chips. A computer architecture textbook model of how chip characteristics affect microprocessor performance is specified and tested in a structural econometric model of microprocessor computing performance. This simple econometric model, using only a small set of explanatory chip characteristics, explains 99% of variance across processor models in performance on commonly used performance benchmarks. This small set of characteristics should clearly be included in any hedonic model of computer or processor prices. Most of these chip characteristics also affect chip production cost, and therefore have an additional rationale for inclusion in a hedonic model that is separate from their demand-side effects on computer performance metrics relevant to users.

Retrospective on VLSI value scaling and lithography

“…For example, VLSI design costs for microprocessors and large systems on chip from the 28-to the 10-nm node have been rising at a rate between 35% to 50% per generation, 32,33 with 10-nm design costs estimated to be in the range $100 to $300 M. Calculating design cost per transistor gives design-productivity improvement rates between 33% to 50% per generation (assuming a doubling number of devices per design generation). A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

“…A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

Retrospective on VLSI value scaling and lithography

“…For example, VLSI design costs for microprocessors and large systems on chip from the 28-to the 10-nm node have been rising at a rate between 35% to 50% per generation, 32,33 with 10-nm design costs estimated to be in the range $100 to $300 M. Calculating design cost per transistor gives design-productivity improvement rates between 33% to 50% per generation (assuming a doubling number of devices per design generation). A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

“…A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

Measuring distortions in international markets

“…They are averaged globally and are based on a large sample of listed semiconductor firms extending beyond the 21 companies studied in this report. Finally, the analysis assumes a central value of 6.5% per annum for the equity risk premium in line with the existing literature, with a range of ± 1 percentage point (Lucas, 2014[88]; Jordà, Schularick and Taylor, 2019 [90]; Fernandez, 2019 [91]).…”

“…This reflects an ex ante approach to assessing the equity investment by comparing the decision, based on the costs and expected returns of the transaction, to the usual investment practice of private investors at the moment the decision to invest is undertaken." 91 Instead of trying to predict the expected future returns of the transaction at the time the investment is made, this report chooses to look at the observed financial performance of government-invested firms for a period of several years following the transaction. Another important difference is that the approach used in this report does not focus on equity injections themselves as one-off, discrete events.…”

Pulse-controlled qubit in semiconductor double quantum dots

“…For example, the same scheme can be used to control a spin qubit by varying the magnetic field B instead of a voltage bias. In this particular case, it is easier to adjust the energy splitting ∆ = 1 2 γB by applying a strong reference magnetic field. Increasing ∆ will result in faster operation.…”

Retrospective on VLSI value scaling and lithography

“…For example, VLSI design costs for microprocessors and large systems on chip from the 28-to the 10-nm node have been rising at a rate between 35% to 50% per generation, 32,33 with 10-nm design costs estimated to be in the range $100 to $300 M. Calculating design cost per transistor gives design-productivity improvement rates between 33% to 50% per generation (assuming a doubling number of devices per design generation). A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

“…A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

Measuring distortions in international markets

“…They are averaged globally and are based on a large sample of listed semiconductor firms extending beyond the 21 companies studied in this report. Finally, the analysis assumes a central value of 6.5% per annum for the equity risk premium in line with the existing literature, with a range of ± 1 percentage point (Lucas, 2014[88]; Jordà, Schularick and Taylor, 2019 [90]; Fernandez, 2019 [91]).…”

“…This reflects an ex ante approach to assessing the equity investment by comparing the decision, based on the costs and expected returns of the transaction, to the usual investment practice of private investors at the moment the decision to invest is undertaken." 91 Instead of trying to predict the expected future returns of the transaction at the time the investment is made, this report chooses to look at the observed financial performance of government-invested firms for a period of several years following the transaction. Another important difference is that the approach used in this report does not focus on equity injections themselves as one-off, discrete events.…”

Pulse-controlled qubit in semiconductor double quantum dots

“…For example, the same scheme can be used to control a spin qubit by varying the magnetic field B instead of a voltage bias. In this particular case, it is easier to adjust the energy splitting ∆ = 1 2 γB by applying a strong reference magnetic field. Increasing ∆ will result in faster operation.…”

Retrospective on VLSI value scaling and lithography

“…For example, VLSI design costs for microprocessors and large systems on chip from the 28-to the 10-nm node have been rising at a rate between 35% to 50% per generation, 32,33 with 10-nm design costs estimated to be in the range $100 to $300 M. Calculating design cost per transistor gives design-productivity improvement rates between 33% to 50% per generation (assuming a doubling number of devices per design generation). A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

“…A similar analysis for photomask-set costs 30,35 (prices) from 130 nm ($450 to $700 K) to 28 nm ($2 to $3 M) reveals a 33% generational decrease in mask-set costs per transistor-despite increasing mask complexity from OPC and RETs. With multipatterning, mask-set costs have accelerated and recent price estimates 30 suggest those costs have been increasing faster than component density.…”

Measuring distortions in international markets

“…They are averaged globally and are based on a large sample of listed semiconductor firms extending beyond the 21 companies studied in this report. Finally, the analysis assumes a central value of 6.5% per annum for the equity risk premium in line with the existing literature, with a range of ± 1 percentage point (Lucas, 2014[88]; Jordà, Schularick and Taylor, 2019 [90]; Fernandez, 2019 [91]).…”

“…This reflects an ex ante approach to assessing the equity investment by comparing the decision, based on the costs and expected returns of the transaction, to the usual investment practice of private investors at the moment the decision to invest is undertaken." 91 Instead of trying to predict the expected future returns of the transaction at the time the investment is made, this report chooses to look at the observed financial performance of government-invested firms for a period of several years following the transaction. Another important difference is that the approach used in this report does not focus on equity injections themselves as one-off, discrete events.…”

Pulse-controlled qubit in semiconductor double quantum dots

“…For example, the same scheme can be used to control a spin qubit by varying the magnetic field B instead of a voltage bias. In this particular case, it is easier to adjust the energy splitting ∆ = 1 2 γB by applying a strong reference magnetic field. Increasing ∆ will result in faster operation.…”