Belief-Propagation Assisted Scheduling in Input-Queued Switches

Abstract

We consider the problem of scheduling the transmission of packets in an input-queued switch. In order to achieve maximum throughput, scheduling algorithms usually employ the queue length as a parameter for determining the priority to serve a given queue. In this work we propose a novel scheme to optimize the performance of a preexisting scheduler. Our main idea is to assist the scheduling decision, considering "messages" rather than queue lengths. Such messages are obtained by running an iterative parallel algorithm, inspired by a rigorous Belief-Propagation approach. We demonstrate that Belief-Propagation-assisted scheduling is able to boost the performance of a given scheduler, reaching almost optimal throughput, even under critical traffic scenarios.

Belief-Propagation-Assisted Scheduling in Input-Queued Switches

“…This is much smaller than OðN 3 Þ, experienced by MWM because of its intrinsic serial nature. The low complexity of WP is also compatible with an efficient hardware implementation, as discussed in our technical report [10].…”

“…From a practical point of view, the interesting fact is that the WP module can be implemented independently of the scheduler and that it is amenable to an efficient parallel implementation. The latter issue goes beyond the scope of the current brief contribution, but it is thoroughly discussed in the aforementioned technical report [10].…”

“…In [9], [10], we also report a theoretical derivation, aimed at explaining the conceptual origin of the algorithm, without resorting to previous knowledge from the theory of graphical models.…”

“…In Section 5, we draw some conclusions. A high-level hardware design of the proposed system is described in [9] and in a more detailed technical report [10].…”

A Load Balancer for a Multi-Stage Router Architecture

“…It is worth emphasizing that it is possible to support even higher line rates by switching to faster hardware. As far as the last point is concerned, Application-Specific Integrated Circuits (ASICs) are usually 4 times faster than FPGA (with a 30 times smaller area) [21,7,6]. The main contributions of this paper are: i) design, implementation and test of advanced low-level packet manipulation mechanisms, ii) integration of an hardware solution into an existing distributed router architecture obtaining performance improvements and iii) identification of a design issue in the NetFPGA board (e.g.…”